Ramakant
Assistant Professor
ramakant@mahindrauniversity.edu.in
Dr. Ramakant Yadav is a member of IEEE and has a teaching experience of more than 9 years. He received his B. Tech. degree in Electronics and Communication Engineering from Chhatrapati Shahu Ji Maharaj University, Kanpur in year 2010. In 2012, he received his M. Tech. degree in Signal Processing specialization from Indian Institute of Technology Guwahati. He completed his Ph.D. program in the EEE department of BITS Pilani, in the area Tunnel Field Effect Transistor in 2022. He joined the EEE department of Mahindra University (MU) as an Assistant Professor on 20th June 2022. Before joining (MU), he has been associated with Birla Institute of Technology and Science (BITS) Pilani, Hyderabad Campus, as an Assistant Professor in the Electrical and Electronics Engineering Department, since Feb. 2016. His research interests include Tunnel FETs, semiconductor devices and VLSI circuit design.
2022
Ph. D. (EEE Department), Semiconductor Devices, Birla Institute of Technology and Science Pilani, 2022.
2012
M. Tech. (EEE Department), Signal Processing, Indian Institute Technology Guwahati, 2012.
2010
B. Tech. (Electronics and Communication Engineering), Chhatrapati Shahu Ji Maharaj University, Kanpur, 2010.
since June 2022
- Assistant Professor, Electrical & Electronics Department, Mahindra University, (since June 2022)
2016-2022
- Assistant Professor, Electrical & Electronics Engineering Department, BITS Pilani, Hyderabad Campus (Feb. 2016 – June 2022)
2012-2016
- Lecturer, Electronics & Communication Engineering Department, RGUKT IIIT R K Valley, Kadapa (July 2012 – Jan. 2016)
Journal articles published
2023
Billel Smaani, Neha Paras, Shiromani Balmukund Rahi, Young Suh Song, Ramakant Yadav, Subham Tayal, Impact of the Self-Heating Effect on Nanosheet Field Effect Transistor Performance', ECS Journal of Solid State Science and Technology, Volume 12, issue 2, pages 021005, Feb 2023, Impact Factor: 2.07. (DOI: 10.1149/2162-8777/acb96b).
2021
- Ramakant Yadav, Surya Shankar Dan, and Simhadri Hariprasad, 'Low and High Vt GOTFET Devices Outperform Standard CMOS Technology in Ternary Logic Applications', IETE Technical Review, issue 38 pp – 1-10, Aug 2021, Impact Factor: 2.20. (https://doi.org/10.1080/02564602.2021.1960903).
- Simhadri Hariprasad, Surya Shankar Dan, Ramakant Yadav, and, Ashutosh Mishra 'Double-Gate Line-Tunneling FET (DGLTFET) Devices for Superior Analog Performance', Wiley International Journal on Circuits Theory and Applications, vol. 49, pp. 2094-2111, April 2021, Impact Factor: 2.038.(https://doi.org/10.1002/cta.3002).
2020
- Ramakant Yadav, Surya Shankar Dan, Sanjay Vidhyadharan and Simhadri Hariprasad, 'Suppression of Ambipolar Behavior and Simultaneous Improvement in RF Performance of Gate-Overlap Tunnel Field Effect Transistor (GOTFET)', Springer Silicon Journal, vol. 13, pp. 1185–1197, July 2020, Impact Factor: 2.67. (https://doi.org/10.1007/s12633-020-00506-1).
- Ramakant Yadav, Surya Shankar Dan, Sanjay Vidhyadharan and Simhadri Hariprasad, 'Innovative multi‐threshold gate‐overlap tunnel FET (GOTFET) devices for superior ultra‐low power digital, ternary and analog circuits at 45 nm technology node', Springer Journal of Computational Electronics. vol. 19, pp. 291-303, January 2020, Impact Factor: 1.807. (https://doi.org/10.1007/s10825-019-01440-1).
- Sanjay Vidhyadharan, Surya Shankar Dan, Ramakant Yadav, and Simhadri Hariprasad, 'An Innovative Ultra-Low Voltage GOTFET based Regenerative-Latch Schmitt Trigger', Elsevier Microelectronics Journal, vol. 104, p. 104879, August 2020, Impact Factor: 1.607. (https://doi.org/10.1016/j.mejo.2020.104879).
- Sanjay Vidhyadharan, Surya Shankar Dan, Abhay S, V, Ramakant Yadav, and Simhadri Hariprasad, 'Novel Gate-Overlap Tunnel FET based Innovative Ultra-Low Power Ternary Flash ADC', Elsevier Integration, the VLSI Journal, vol. 73, pp. 101-113, April 2020, Impact Factor: 1.211. (https://doi.org/10.1016/j.vlsi.2020.03.006).
- Sanjay Vidhyadharan, Surya Shankar Dan, Ramakant Yadav, and Simhadri Hariprasad, 'A Novel Ultra-Low Power Gate-Overlap Tunnel FET (GOTFET) Dynamic Adder', Taylor and Francis International Journal of Electronics, vol. 107, no. 10, pp. 1663-1681, Mar 2020, Impact Factor: 1.336. (https://doi.org/10.1080/00207217.2020.1740800).
2019
- Sanjay Vidhyadharan, Ramakant Yadav, Simhadri Hariprasad and Surya Shankar Dan, 'A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications', Springer Analog Integrated Circuits and Signal Processing, Vol. 101, pp. 109-117, June 2019, Impact Factor: 1.337. (https://doi.org/10.1007/s10470-019-01487-x).
- Sanjay Vidhyadharan, Ramakant Yadav, Simhadri Hariprasad and Surya Shankar Dan, 'An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications', Springer Analog Integrated Circuits and Signal Processing, Vol. 102, pp. 111-123, November 2019, Impact Factor: 1.337 (https://doi.org/10.1007/s10470-019-01561-4).
Book chapters published:
2023
2019
- Ramakant, Sanjay Vidhyadharan, Gangishetty Akhilesh, Vaibhav Gupta, Anand Ravi and Surya Shankar Dan, 'Part I: Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better than the Current Standard 45 nm CMOS Technology', Springer Proceedings in Physics, vol. 215, pp. 611–618, Feb 2019, R. K. Sharma and D. S. Rawal, Eds. Cham: Springer International Publishing. (https://doi.org/10.1007/978-3-319-97604-4_95).
- Sanjay Vidhyadharan, Ramakant, G. Akhilesh, Vaibhav Gupta, Anand Ravi and Surya Shankar Dan , 'Part II: Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard45 nm CMOS Technology using Device & Circuit Co-Simulation Methodology', Springer Proceedings in Physics, vol. 215, pp. 619-628, Feb 2019, R. K. Sharma and D. S. Rawal, Eds. Cham: Springer International Publishing. (https://doi.org/10.100/978-3-319-97604-4_96).
Conference Papers published
2019
- Ramakant, Sanjay Vidhyadharan, A. Krishna Shyam, Mohit P. Hirpara, Tanmay Chaudhary and Surya Shankar Dan, 'Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications', 32nd International Conference on VLSI Design (VLSID 2019), May 2019, pp – 419 - 424 New Delhi. (https://doi.org/10.1109/VLSID.2019.00090).
- Sanjay Vidhyadharan, Ramakant Yadav, Abhay SV, A. Krishna Shyam, Mohit P. Hirpara and Surya Shankar Dan, 'An Efficient Design Approach for Implementation of 2-bit Ternary Flash ADC Using Optimized Complementary TFET Devices', 32nd International Conference on VLSI Design (VLSID 2019), pp-401-406 New Delhi. (https://doi.org/10.1109/VLSID.2019.00087).
2015
- Ramakant, Noor-e-Karishma Shaik, Lathasree Veerapalli, 'Sign Language Recognition Through Fusion of 5-DT Data Glove and Camera Based Information', 2015 IEEE International Advance Computing Conference (IACC), pp. 639-643, July 2015. (https://doi.org/10.1109/IADCC.2015.7154785).
Research Projects
- Project Title: Design and Performance Investigation of Negative Capacitance Tunnel Field Effect Transistor
(NC-TFET) for Ultra-Lowe Power Binary, Ternary, and Analog VLSI Applications. - Name of the investigators: Dr. Ramakant Yadav (PI), Prof. Ram Mohan Vemuri (Co-PI)
- Sponsoring Agency: Seed grant from Mahindra University, India
- Amount granted: 5.5 Lakhs Rs.
- Period: 2 Years
- Status: Ongoing
Research Areas:
- Development of Tunnel FETs for low power Digital and Ternary logic applications.
- Semiconductor devices beyond CMOS technology.
- A Study of the Memristors and Applications.
